/*
 * Copyright (C) 2018 Hisilicon Limited.
 *
 * this program is for pcie nvme comm
 *
 * This program is free software; you can redistribute it and /or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version
 */

#include <asm/io.h>

#include "nvme_drv.h"

void devdrv_nvme_reg_wr(void __iomem *io_base, u32 offset, u32 val)
{
    writel(val, io_base + offset);
}

void devdrv_nvme_reg_rd(const void __iomem *io_base, u32 offset, u32 *val)
{
    *val = readl(io_base + offset);
}

void devdrv_set_admin_sq_base(void __iomem *io_base, u64 val)
{
    devdrv_nvme_reg_wr(io_base, DEVDRV_MSG_SQ_BASE_ADDR_H, (u32)(val >> 32));
    devdrv_nvme_reg_wr(io_base, DEVDRV_MSG_SQ_BASE_ADDR_L, (u32)val);
}

void devdrv_get_admin_sq_base(const void __iomem *io_base, u64 *val)
{
    u32 regval;

    devdrv_nvme_reg_rd(io_base, DEVDRV_MSG_SQ_BASE_ADDR_H, &regval);
    *val = (u64)regval << 32;
    devdrv_nvme_reg_rd(io_base, DEVDRV_MSG_SQ_BASE_ADDR_L, &regval);
    *val |= regval;
}

void devdrv_set_sq_doorbell(void __iomem *io_base, u32 val)
{
    devdrv_nvme_reg_wr(io_base, 0, val);
}

void devdrv_set_cq_doorbell(void __iomem *io_base, u32 val)
{
    devdrv_nvme_reg_wr(io_base, DEVDRV_MSG_CHAN_DB_OFFSET, val);
}
